1. Field of the Invention
The present invention relates to a process of manufacturing MIS (Metal . Insulator . Semiconductor) type FETs (Field Effect Transistor), and more particularly, to a process of manufacturing micro MIS type FETs having a short channel layer between the source/drain regions.
2. Description of the Related Art
In accordance with the miniaturization of semiconductor devices, the impurity concentration of the semiconductor substrate is liable to be increased by the scale down law. Semiconductor devices operated at low temperatures are being investigated in order to lower the supply voltage or the threshold voltage in micro semiconductor devices. The scale down law is described in details in VLSI Electronics: Microstructure Science, Vol. 18, pp. 1-9, edited by N. G. Einspruch and G. S. Gildenblat and published by Academic Press, Inc.
FIGS. 15A-15F are sectional views showing the structure of and the process for manufacturing a conventional micro n-channel MISFET with a channel of approximately 0.3 .mu.m in length and approximately 10 .mu.m in width.
Referring to FIG. 15A, boron ions B.sup.+ are implanted into a p-type silicon substrate 101 (normally having an impurity concentration of 10.sup.15 /cm.sup.3) as indicated by the arrows at the acceleration voltage of approximately 100 KeV and with the dose rate of approximately 5.times.10.sup.13 /cm.sup.2. Then, the implanted impurities are diffused into the substrate at a temperature higher than 1000.degree. C. for several hours, resulting in the impurity concentration distribution shown in FIG. 16A. FIG. 16A indicates the impurity concentration distribution in substrate 101 at a section taken along line 16A--16A of FIG. 15A. The abscissa axis represents the depth (nm) from the surface of silicon substrate 101, while the ordinate axis represents the impurity concentration (cm.sup.-3). It can be seen that the impurity concentration in the vicinity of the surface of silicon substrate 101 is increased to approximately 1.times.10.sup.17 /cm.sup.3.
Referring to FIG. 15B, an isolation oxide film 102 with a thickness of more than 400 nm is formed by thermal oxidation. Beneath the isolation oxide film 102, boron ions have been previously selectively implanted to form a channel cut region 103 having an impurity concentration of approximately 1.times.10.sup.18 /cm.sup.3.
Referring to FIG. 15C, boron ions B.sup.+ are implanted into the shallow region of substrate 101 as indicated by the arrows at an acceleration voltage of 30-40 KeV and with the dose rate of approximately 2.times.10.sup.13 /cm.sup.2 for the purpose of controlling threshold voltages. This results in the impurity concentration distribution as illustrated in FIG. 16B. FIG. 16B indicates an impurity concentration distribution in substrate 101 at a section taking along line 16B--16B of FIG. 15C. It is noted that a buried peak of the impurity concentration exceeding 1.times.10.sup.18 /cm.sup.3 is formed in the vicinity of the surface of substrate 101.
Referring to FIG. 15D, a gate insulating oxide film 104 with the thickness of approximately 7 nm is formed. On the gate insulating film 104, an n-type polycrystalline silicon gate electrode 105 with the thickness of approximately 300 nm is formed.
Referring to FIG. 15E, arsenic ions are implanted into substrate 101 at the acceleration voltage of 50 KeV and with the dose rate of 1.times.10.sup.15 -5.times.10.sup.15 /cm.sup.2 using gate electrode 105 and isolation oxide film 102 as masks. The implanted arsenic ions are annealed for about 30 minutes at the temperature of 800.degree. C.-900.degree. C. so that a source/drain region 106 is formed. The boron concentration within substrate 101 at a section taken along line 16C--16C of FIG. 15E is as shown in FIG. 16C. It is seen that the buried peak of the boron concentration in the vicinity of the surface of substrate 101 is slightly lower than 1.times.10.sup.18 /cm.sup.3.
Referring to FIG. 15F, an interlayer insulating film 107 is deposited to the thickness of approximately 600 nm, and a contact hole 107a is formed by etching. Thereafter, a layer of metal such as aluminum is deposited, by which a source/drain electrode 108 is formed by means of patterning. This completes the formation of a micro n-channel MISFET by prior art.
FIG. 17A shows the relationship between gate voltage V.sub.G and drain current I.sub.D of the N channel MISFET of FIG. 15F. The abscissa represents gate voltage V.sub.G (V), while the ordinate represents drain current I.sub.D (Ma). In FIG. 17A, it is assumed that the substrate voltage and the source voltage are 0 V, while the drain potential V.sub.D is 0.1 V. When drain voltage V.sub.D =0.1 V, the transconductance g.sub.m of the MISFET is represented as: ##EQU1## which indicates that the conventional micro n-channel MISFET with a channel of approximately 0.3 .mu.m in length and approximately 10 .mu.m in width has a conductance g.sub.m of approximately 0.480 Ms (S=1/.OMEGA.).
Referring to FIG. 17B, the relationship between drain voltage V.sub.D and drain current I.sub.D in the MISFET of FIG. 15F is depicted. The abscissa represents drain voltage V.sub.D (V), while the ordinate represents drain current I.sub.D (Ma). In FIG. 17B, the substrate potential and the source potential are 0 V, while gate voltage V.sub.G is 5 V.
Referring to FIG. 18A, an inverter circuit comprising a conventional n-channel MISFET as a driver is shown. The inverter circuit comprises an input terminal 1, a power supply terminal 2, a load resistor 3, a driver MISFET 4, and an output terminal 5.
FIG. 18B shows the operating characteristics of the n-channel MISFET 4 in the inverter of FIG. 18A in conjunction with its relation to the operating characteristics of various load resistors 3. The abscissa represents drain voltage V.sub.D (V), while the ordinate represents drain current I.sub.D (Ma). In FIG. 18B, source voltage V.sub.DD has been selected to be 3 V, with lines 3a and 3c representing the instances of a low resistance of 670.OMEGA. and a high resistance of 3000.OMEGA. of load 3, respectively. Line 3c denotes the case where the resistance of load 3 is slightly lower than the ON resistance of driver FET 4. According to Kirchhoff's law, current I.sub.D which flows through the drain of driver FET 4 is equal to the current which flows through load resistor 3, and the sum of the voltage of drain voltage V.sub.D in driver FET 4 and the voltage across load resistor 3 is equal to source voltage V.sub.DD, in a steady state. Therefore, the operating point of the inverter of FIG. 18A is at the crossing point of the curve and the linear line of FIG. 18B.
FIG. 18C shows the static characteristics of output voltage Vout (V) at output terminal 5 when input voltage Vin (V) is supplied to the input terminal of the driver in FIG. 18A, while FIG. 18D shows the static characteristics of the consumption current I.sub.D (mA) which flows through the drain of driver FET 4 at that time. In these graphs, curves 3a, 3b, and 3c represent the instances where load 3 has a low resistance, a medium level resistance, and a high resistance, respectively. If C.sub.0 is the capacity of the fan out of the inverter, charge Q accumulated for time t (sec) is given by the following equation (1): ##EQU2##
When the output capacitance Co is constant, this equation indicates that the greater consumption current I.sub.D (t) is, the faster the output potential of the inverter will rise, resulting in a faster operating rate of the inverter. Here, Iout(t) represents the current passing through the output terminal and then Iout(t) becomes large when I.sub.D (t) is large. Therefore, from the standpoint of the operating rate of the inverter, it is preferable to have the resistance of load 3 as low as possible, as can be appreciated from FIG. 18D. However, the output voltage Vout of the inverter should have a great difference between the ON voltage and the OFF voltage in order to prevent the malfunction of the digital circuit comprising the inverter (in practice, curve 3b in FIG. 18C is preferred). In the case that the load resistance is small, I.sub.D (t) does not increase so much, because it is limited in the saturation current (I.sub.D.sat). At this time, on the other hand, the difference between the ON voltage and OFF voltage becomes small, as seen in FIG. 18C. In other words, when the load resistance is small, operational speed of the inverter is hardly increased and the inverter is liable to be adversely affected by noises. Consequently, it would be most preferable for load 3 to have a resistance similar to ON resistance which is defined as {V.sub.D -V.sub.D .multidot.sat(V.sub.G =V.sub.D)}/I.sub.D .multidot.sat where V.sub.D .multidot.sat denotes saturation voltage of driver FET 4 to allow the high speed operation of the inverter as well as preventing the malfunction of the digital circuit. In this case, the value of Iout(t) can be similar to that in the case of the low load resistance and then the ON-OFF voltage ratio can be similar to that in the case of the high load resistance. In other word, an inverter can be obtained which has a high operational speed and does not cause malfunction. If the ON resistance of driver FET 4 is further lowered, the resistance of load 3 also can be lowered at the equal amount while preventing the malfunction of the digital circuit and increase further the operating speed of the inverter.
Referring to FIG. 19, the relation of the impurity concentration with the mobility of the carriers in the silicon at room temperature is shown. The abscissa gives the total impurity concentration (cm.sup.-3), while the ordinate gives the mobility (cm.sup.-2 /V.multidot.sec). Curve A represents the mobility of the electrons and curve B represents the mobility of the holes. As mentioned before, the impurity concentration of the semiconductor substrate is liable to be increased by the scale down law in accordance with the miniaturization of semiconductor devices. However, as can be seen from FIG. 19, when the impurity concentration of the substrate exceeds approximately 10.sup.16 /cm.sup.3, the mobility of the carriers rapidly decrease due to the transverse electric field at room temperature and due to the scattering of the impurities at cryogenic temperature. Accordingly, the improvement in the operating rate by miniaturization of conventional MISFETs will be limited because of the drop in transconductance g.sub.m.
In accordance with the scale down law, the supply voltage should also be lowered corresponding to the miniaturization of the semiconductor device. This is because it is necessary to restrict the heating value in the high density integrated circuits comprising a number of micro semiconductor devices, and because micro semiconductor devices are liable to have low breakdown voltages. In order to lower the supply voltage, the threshold voltage of the MISFET must also be lowered, leading to the necessity of suppressing the subthreshold swing to a small range. The subthreshold swing S is given as S.tbd..differential.V.sub.G /.differential.(log I.sub.D) and described in details by N. Shigyo et al. in IEEE Transactions on Electron Devices, Vol. 35, 1988, pp.945-951. However, at the room temperature of T=300.degree. K., the subthreshold swing decreases to only (Kt/q) log.sub.e 10.apprxeq.60 mV/decade even at its most ideal state. Therefore, the minimum threshold voltage Vth allowed to suppress the current leakage of the MISFET is decreased to only the degree of 0.5 V-0.6 V at room temperature. Thus, the operation of semiconductor devices at low temperatures is considered. At a low temperature, the lattice vibration is suppressed, whereby the effect of lattice scattering with respect to the mobility of the electrons is reduced. Hence, the effect of the scattering of the impurities in relation to the mobility of the electrons will become a relatively critical problem.
In addition, the input/output characteristics, i.e. the transfer characteristics in FIG. 18C show that the slopes of the transient region from on-state to off-state are relatively gentle, which means that there is the problem of the inverter being susceptible to the effect of external noise. Furthermore, since the logical amplitude of the output voltage (voltage range corresponding to logic "0" or "1") in conventional inverters is relatively small, the noise margin is small, which means that it is susceptible to noise effects. It is needless to say that the problem of noise is critical as semiconductor devices becomes more miniaturized, and is aggravated by the reduction of the source voltage and threshold voltage.